| 摘要 |
A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multiple signals and, based upon those timing characteristics, vary which clock-related signal is output. The improvement relates in part to the incorporation of a clock divider that reduces the frequency of the clock signals utilized by the system. Due to the incorporation of the clock divider and an edge recovery device, attenuation, power dissipation and duty cycle distortion associated with propagation of the clock signal(s) are reduced. Further, the reduction in frequency of the clock signals allows for numerous differently-phased clock signals to be generated within the system, which allows for finer timing comparisons to be performed, thus allowing for finer selections to be made in relation to which clock-related signal is output.
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