| 摘要 |
A Data Throttling method duplicates the full-speed transmission of data so that it appears to be transmitting at a 10 Mhz rate. Additional storage elements and multiplexers are added along the data path but this completely eliminates undesirable complexity in the clock tree. In a two-bit application, data is received and transmitted two bits at a time, and yet the output 10 Mhz data rate is maintained. For an even ratio between the system clock rate and the 10 Mhz clock signal rate, bit 0 is transmitted for half the time and bit 1 is transmitted for the other half of the time. But if the full-speed clock rate is an odd multiple of 10 Mhz, then there will be a "split cycle" including one bit 0 and one bit 1.
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