TESTABLE INTEGRATED CIRCUIT DIE AND INTEGRATED CIRCUIT PACKAGE

摘要

An integrated circuit die (100) is disclosed that comprises a functional block (110) and a test module for testing the functional block. The test module comprises test pattern decompression logic (120) for receiving a compressed test pattern and providing the functional block (110) with the decompressed test pattern and test result compression logic (130) for compressing a test result received from the functional block(110).The integrated circuit die (100) further comprises a test access port(TAP) (140) such as an IEEE 1149.1 compliant TAP. The test pattern decompression logic (120) is coupled to the test data input of the TAP (140) and the result compression logic (130) is coupled to test data output of the TAP (140) to facilitate shifting in/out of compressed test data under control of the test clock. The TAP instruction register (150) is responsiveto a dedicated instruction for activating the test module. Consequently, an on-chip test compression arrangement is provided that can be fully controlled through the TAP (140).