| 摘要 |
A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The first NOT gate is coupled between a positive output terminal of the last second flip-flop and the first flip-flop. The second NOT gate is coupled between the positive output terminal of the last second flip-flop and the circuit. The first NOT gate and the second NOT gate are controlled by the mode control signal for enabling. If N is an odd number, the circuit includes a wire, and if N is an even number, the circuit includes a third NOT gate.
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