发明名称 |
Method For Optimized Automatic Clock Gating |
摘要 |
A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.
|
申请公布号 |
US2008301594(A1) |
申请公布日期 |
2008.12.04 |
申请号 |
US20080128574 |
申请日期 |
2008.05.28 |
申请人 |
MAGMA DESIGN AUTOMATION, INC. |
发明人 |
JIANG YUNJIAN (WILLIAM);SRINIVASAN ARVIND;BANERJEE JOY;LI YINGHUA;DAS PARTHA;CHAUDHURI SAMIT |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|