发明名称 |
HIGH FREQUENCY DIVIDER STATE CORRECTION CIRCUIT |
摘要 |
The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
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申请公布号 |
US2008301503(A1) |
申请公布日期 |
2008.12.04 |
申请号 |
US20080187517 |
申请日期 |
2008.08.07 |
申请人 |
BOERSTLER DAVID WILLIAM;LUKES ERIC JOHN;KIHARA HIROKI;STROM JAMES DAVID |
发明人 |
BOERSTLER DAVID WILLIAM;LUKES ERIC JOHN;KIHARA HIROKI;STROM JAMES DAVID |
分类号 |
G06F11/28;G01R31/28;G06F7/58;H03K3/037;H03K3/12;H03K3/286;H03K3/356;H03K21/40 |
主分类号 |
G06F11/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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