| 摘要 |
<p>A microprocessor apparatus is provided that enables exclusive prefetch of a block of data from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended block prefetch instruction into a micro instruction sequence that directs a microprocessor to prefetch a specified number of cache line in an exclusive state. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the specified number of cache lines in the exclusive state. <IMAGE></p> |
