| 摘要 |
A PCB or package substrate comprises a number of metal layers interleaved between a number of dielectric layers to form a stack and an electronic signal interconnect path comprising a plurality of micro-vias, each micro-via connecting a pair of adjacent metal layers. The micro-vias are positioned in a staggered arrangement in relation to each other, so that vertically adjacent micro-vias in the stack do not coincide in their alignment. This reduces the level of excess capacitance in the vicinity of the vias, and so causes their characteristic impedance to be closer to the 50 Ohm value implemented for the traces. In a further invention, the geometry of the landing pad associated with the via is arranged to minimize the area of the pad whilst maintaining mechanical stability (fig 5). |
