发明名称 SCAN TEST CIRCUIT, SCAN TEST CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To solve a problem that a conventional delay test method complicates generation of data for failure inspection as the data for failure inspection for a delay test requires expected values after application of two clocks, and complicates a circuit for constructing an inside of a scan control circuit. SOLUTION: The scan test circuit includes an FF for control for inputting a control signal, and a scan pass chain of a storage element where an output is in a shift operation mode at a first state value and is in a normal operation mode at a second state value. The FF for control outputs the second state value to the plurality of the storage elements in synchronization with a first clock pulse after transition of a clock given to the plurality of the storage elements when the control signal transits from the first to the second state value. When the control signal transits from the second to the first state value, the first state value is output to the plurality of scan storage elements at a timing when the control signal transits. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008275479(A) 申请公布日期 2008.11.13
申请号 JP20070120178 申请日期 2007.04.27
申请人 NEC ELECTRONICS CORP 发明人 MIKAMI KIYOSHI
分类号 G01R31/28 主分类号 G01R31/28
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