发明名称 Intergrated Circuit Self-Test Architecture
摘要 An integrated circuit ( 1 ) comprises a monitor (M 1 , M 3 , M 3 ) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit ( 1 ); and a self test controller ( 28 ) connected to receive monitor data from the monitor (M 1 , M 2 , M 3 ). The self-test controller is also operable to output self test data from the integrated circuit. The monitor includes an output shift register (SR 1 , SR 2 , SR 3 ) and is operable to output monitor data through the shift register (SR 1 , SR 2 , SR 3 ). Such a system enables simplified communication of system self test results on an integrated circuit.
申请公布号 US2008272797(A1) 申请公布日期 2008.11.06
申请号 US20050720317 申请日期 2005.11.23
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V. 发明人 PELGROM MARCELLINUS JOHANNES MARIA;VEENDRICK HENDRICUS JOSEPH MARIA
分类号 G01R31/3187 主分类号 G01R31/3187
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