| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To solve such a problem that increment of a rewriting time and deterioration of reliability are caused by occurrence of variation of rewriting speed in accordance with a position of a memory cell in a nonvolatile memory cell array. <P>SOLUTION: When reduction of drain voltage is caused in the center of a memory cell array 101 due to voltage drop in bit lines B0 to B4, a voltage correcting circuit 102 correcting gate voltage applied to the memory cells 103a, 103b in accordance with a position of a memory cell is arranged between the memory cell array 101 and a word line driving circuit 104. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
