发明名称 |
Contact resistance and capacitance for semiconductor devices |
摘要 |
A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.
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申请公布号 |
US7441218(B2) |
申请公布日期 |
2008.10.21 |
申请号 |
US20060440657 |
申请日期 |
2006.05.24 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
SAVITHRI NAGARAJ N.;SHAH DHARIN NAYESHBHAI;GURUMURTHY GIRISHANKAR |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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