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发明名称
半导体装置及其制造方法
摘要
提供可以低电压进行资料之写入与抹除的半导体装置及其制造方法。具备:Si层5,介由绝缘膜3形成于矽基板1上;Si层9,介由绝缘膜7形成于Si层5上;PMOS20,形成于Si层5之至少1个侧面;及NMOS30,形成于Si层9之至少1个侧面;PMOS20及NMOS30,系具有共通之控制闸极17及共通之浮态闸极13。共通之浮态闸极13,系自Si层5之侧面至Si层9之侧面被连续设置。依本发明,对共通之浮态闸极13之写入与抹除,可藉由电子与电洞之2种载子之供给而实现。
申请公布号
TW200840055
申请公布日期
2008.10.01
申请号
TW096145001
申请日期
2007.11.27
申请人
精工爱普生股份有限公司
发明人
加藤树理
分类号
H01L29/788(2006.01);H01L29/792(2006.01);H01L27/115(2006.01)
主分类号
H01L29/788(2006.01)
代理机构
代理人
林志刚
主权项
地址
日本
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