| 摘要 |
An integrated circuit (100) is disclosed comprising a plurality of circuit portions (120, 140) including a first circuit portion (120) coupled to switchable power means (VDD2, VSS) for selectively switching the first circuit portion (120) between a powered down state and a powered up state. The first circuit portion (120) has a plurality of inputs (124) and a plurality of outputs (122), with each output (122) being coupled to an input (144) of another circuit portion(140) via a signal path (130) comprising an output buffer (126) arranged to adopt a high impedance state in the powered down state. Each signal path (130) to a further circuit portion (140) further comprises, between its output buffer (126) and its associated input (144), a clamp (132) coupled to further power means (VDD) for clamping the signal path (130) to a fixed logic value during said powered down state. This arrangement provides well-defined values on the signal lines (130) connected to the outputs (122) of a powered down circuit portion (120) without the need for additional control logic. |
