发明名称 Memory cell having combination raised source and drain and method of fabricating same
摘要 A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of raised bitlines, where the bitlines have a lower portion formed by a first process and an upper portion formed by a second process.
申请公布号 US7414277(B1) 申请公布日期 2008.08.19
申请号 US20050112884 申请日期 2005.04.22
申请人 SPANSION, LLC 发明人 MELIK-MARTIROSIAN ASHOT;ORIMOTO TAKASHI;RAMSBEY MARK T.
分类号 H01L21/336 主分类号 H01L21/336
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