FLIP CHIP PACKAGING METHOD USING DOUBLE LAYER TYPE WAFER LEVEL UNDERFILL AND FLIP CHIP PACKAGE AND SEMICONDUCTOR DEVICE THEREOF

摘要

A flip chip packaging method using a double layer type wafer level underfill, a flip chip package manufactured by the same, and a semiconductor device are provided to improve the reliability of an electrical and mechanical interconnection by restraining the generation of delamination and crack. A double layer type underfill layer having a different hardening temperature is formed on a surface of a semiconductor wafer on which a solder bump pattern(S110) is formed. A B-stage process is performed on the underfill layer in order to harden one layer of the double layer having a hardening temperature relatively lower than that of the other layer of the double layer of the underfill layer(S120). The semiconductor wafer is diced in a chip unit(S130). The chip from the semiconductor wafer through the dicing process is arranged on a substrate so as to direct a surface of the underfill layer to a surface of the substrate(S140). A reflow process is performed at temperature that hardens all of the double layer of the underfill layer(S150).