CIRCUIT AND TECHNIQUE FOR ADJUSTING AND ACCURATELY CONTROLLING CLOCK DUTY CYCLES IN INTEGRATED CIRCUIT DEVICES

摘要

A circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices in which only N-channel current regulating transistors are used in the voltage-controlled inverters and both the rising and falling edges can be adjusted by cascading two such inverters. The potential for cascading of these inverters allows for additional accuracy to be achieved.