发明名称 Calculation apparatus provided with a plurality of calculating units which access a single memory
摘要 <p>A calculation apparatus comprises a plurality of processing units that processes a plurality of predetermined calculation processes each composed of steps, respectively, and a memory device to which the plurality of processing units are accessible. Specific information that specifies a step that should be executed next among steps of each of the calculation process is memorized in the memory device. In each of the processing units, only when a step specified by the specific information should be executed by that processing unit, the specified step is executed, and the specific information is updated to allow the next step to be executed. This is repeated for all the steps of each calculation process assigned to the plurality of processing units. Each processing unit will not execute steps until the specific information shows that a step specified by the specific information is for the processing unit.</p>
申请公布号 EP1953643(A2) 申请公布日期 2008.08.06
申请号 EP20080001848 申请日期 2008.01.31
申请人 DENSO CORPORATION 发明人 OHI, MASAYA;YAMAMOTO, HIROTAKA
分类号 G06F9/52;G06F9/46 主分类号 G06F9/52
代理机构 代理人
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