发明名称 |
SYSTEM AND CIRCUIT FOR CONSTRUCTING A SYNCHRONOUS SIGNAL DIAGRAM FROM ASYNCHRONOUSLY SAMPLED DATA |
摘要 |
A system and circuit for constructing a synchronous signal diagram from asynchronous sampled data provides a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase to find a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.
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申请公布号 |
US2008177489(A1) |
申请公布日期 |
2008.07.24 |
申请号 |
US20080055317 |
申请日期 |
2008.03.26 |
申请人 |
CRANFORD HAYDEN C;GEBARA FADI H;SCHAUB JEREMY D |
发明人 |
CRANFORD HAYDEN C.;GEBARA FADI H.;SCHAUB JEREMY D. |
分类号 |
G01R13/00;G01R29/26;G06F17/18 |
主分类号 |
G01R13/00 |
代理机构 |
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