A MULTI-TRANSISTOR BASED NON-VOLATILE MEMORY CELL WITH DUAL THRESHOLD VOLTAGE

摘要

A multi-transistor based non- volatile memory cell Ml arranged on a semiconductor substrate 1 includes at least one access transistor ATI; AT2; AT2'; AT2" and at least one memory transistor TM2a; TM2b; TM2c; TM2d. The at least one access transistor is a "normally-off ' transistor and includes first and second diffusion regions Sl, S2, an access channel region Rl, and an access gate AG. The access channel region is intermediate the first and second diffusion regions. The at least one memory transistor includes third and fourth diffusion regions S2, S3, a channel region R2, a charge trapping element O1-N-O2 and a control gate CG. The channel region is intermediate the third and fourth diffusion regions, and the charge trapping element is above the channel region with the control gate being arranged above the charge trapping element. The semiconductor substrate is of a first conductivity type. The at least one memory transistor is provided with a memory threshold voltage window with an upper limit above and a lower limit below zero Volt.