| 摘要 |
A system in which an overdrive period in a DRAM may be provided without providing for accurate delay time. There are provided MOS transistor TP 1 , capacitor C 1 , MOS transistor TP 2 , and control circuit. MOS transistor TP 1 is turned on when overdriving begins, and is designed to supply voltage of power supply VDD 1 to parallel-connected sense amplifiers. Capacitor C 1 accumulates electrical charges referenced to in association with electrical charges supplied to sense the amplifiers via MOS transistor TP 1 . MOS transistor TP 2 is turned on when overdriving begins, to supply voltage of power supply VDD 1 to capacitor C 1 . The control circuit controls so that MOS transistors TP 1 , TP 2 are turned off when the capacitor potential has reached voltage VREF 1 . There is also provided a MOS transistor turned on after the MOS transistors TP 1 , TP 2 are turned off to supply a power supply voltage equal to the voltage VREF 1 to the plural sense amplifiers.
|
