发明名称 Delta-sigma PLL using fractional divider from a multiphase ring oscillator
摘要 A disk drive controller includes a servo system operable to associate a time stamp with an arrival of a servo wedge, a firmware loop and core PLLs in the read channel. The firmware loop is operable to determine a period between the arrival of a pair of consecutive servo wedges and produce a desired frequency of when to read/write data to disk based on the period between the arrival of a pair of consecutive servo wedges. Processing circuitry is operable to adjust a clock signal, wherein the clock signal itself is not locked to the data and produce a fine control signal for the core PLLs in the read channel. These core PLLs are operable to determine a phase and/or frequency associated with when an analog signal is sampled and/or written to disk, wherein these core PLLs comprises Fractional N Sigma Delta PLLs.
申请公布号 US2008158711(A1) 申请公布日期 2008.07.03
申请号 US20070965777 申请日期 2007.12.28
申请人 BROADCOM CORPORATION 发明人 BLISS WILLIAM GENE;CHAMBERS MARK
分类号 G11B21/04 主分类号 G11B21/04
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