| 摘要 |
A memory cell array includes a plurality of memory cells arranged at intersections of bitline pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line, a first node electrode for data-storage connected to the other main electrode of the first transistor, a second node electrode for data-storage connected to the other main electrode of the second transistor, and a shield electrode formed surrounding the first and second node electrodes. The first and second transistors have respective gates both connected to an identical word line, and the first and second bit lines are connected to an identical sense amp. The first and second node electrodes, the first and second bit lines, the word line and the shield electrode are isolated from each other using insulating films.
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