| 摘要 |
A CMOS FET device having an enhanced performance is described by taking advantage of known dual-stress-liner effects and by making use of compressive nitride in an appropriate geometric configuration to induce compressive stress in the n-FET channel, and a tensile stress in the p-FET. The stress enhancement is designed to be insensitive to PC pitch, and to increase by reducing the height of the polysilicon stack, such that scalability contributes to the stated performance improvement. The n-FET leverages higher stress values that are obtainable in the compressive liners to be greater than 3 GPa, compared to less than 1.5 GPa for tensile liners.
|
