发明名称 ERASE CIRCUIT OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device that can reduce a chip area without complicating control for erasing processing in erasing processing in memory cell block units and without providing a boundary area for electrically insulating one memory cell block from the other. <P>SOLUTION: The nonvolatile semiconductor memory device in which memory cells are arranged in a matrix shape in row and column directions in a second conductive type well region formed in a first conductive type semiconductor substrate, and a memory cell allay is formed by connecting control gates of memory cells in the same row to a common word line, divides the memory cell array into a plurality of memory cell blocks configured with a plurality of word lines and performs erasing processing in memory cell block units. The nonvolatile semiconductor memory device performs erasing processing by applying a positive voltage for erasure to the well region, a negative voltage with the same value as the positive voltage for erasure to all the word lines in blocks to be erased, a positive voltage for erasure to control gates of all the memory cells included in memory cell blocks except the blocks to be erased. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008146800(A) 申请公布日期 2008.06.26
申请号 JP20070030701 申请日期 2007.02.09
申请人 SHARP CORP 发明人 KAWASAKI YOICHI
分类号 G11C16/06;G11C16/02;G11C16/04;H01L21/8247;H01L27/115;H01L29/788;H01L29/792 主分类号 G11C16/06
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