| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a data reproducing device which stably generates a clock with satisfactory accuracy even in the case of drastic deterioration in the resolution of a reproduction signal and uses high-speed and stable data PLL. <P>SOLUTION: The data reproducing device comprises; an A/D converter 104 which subjects the output signal of a pickup 102 to analog/digital conversion at a prescribed clock; a waveform equalization circuit 105 which equalizes the outputs signal of the A/D converter 104 to desired characteristics; a maximum likelihood decoding circuit 106 which subjects the output signal of the waveform equalization circuit 105 to maximum likelihood decoding; a phase error detection circuit 107 which detects the phase error of the clock; an equalization error detection circuit 110 which detects the equalization error, an adder 111 which adds the output signal of the phase error detection circuit 107 and the equalization error detection circuit 110; and a voltage control oscillator 114 which is controlled by the output signal of the adder 111 and generates the clock. <P>COPYRIGHT: (C)2008,JPO&INPIT |
