发明名称 SEMICONDUCTOR DEVICE
摘要 <p>In a trap-type memory element, a withstand voltage is increased and a read current is increased, while suppressing a punch through current. On a p-type semiconductor substrate (1), a first gate laminate structure and a second gate laminate structure are formed. The first gate laminate structure is composed of a first insulating film (11), including a trap layer, and a first conductor (9). The second gate laminate structure is composed of a second insulating film (12), including a work function controlling metal added insulating film layer (13) in at least an upper layer not containing the trap layer; and a second conductor (10). A source/drain region (2) and a source/drain region (3) are formed to sandwich the first gate laminate structure and the second gate laminate structure. The effective work function of the second gate laminate structure is higher than that of the first gate laminate structure.</p>
申请公布号 WO2008075656(A1) 申请公布日期 2008.06.26
申请号 WO2007JP74258 申请日期 2007.12.17
申请人 NEC CORPORATION;TERAI, MASAYUKI 发明人 TERAI, MASAYUKI
分类号 H01L21/8247;H01L27/115;H01L29/788;H01L29/792 主分类号 H01L21/8247
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