发明名称
摘要 <p>System to control a pre-charge level of a dual bit cell in a memory device. The system includes apparatus comprising a first terminal coupled between first and second memory cells, and a second terminal coupled to the second memory cell. The apparatus also comprises a mirror circuit coupled to the first and second terminals, wherein the mirror circuit operates to maintain the same voltage level on the first and second terminals.</p>
申请公布号 JP4105976(B2) 申请公布日期 2008.06.25
申请号 JP20030122155 申请日期 2003.04.25
申请人 发明人
分类号 G11C16/06;G11C7/12;G11C16/02 主分类号 G11C16/06
代理机构 代理人
主权项
地址