发明名称 Method and apparatus of cache assisted error detection and correction in memory
摘要 A memory and a method of correcting and detecting an error in a codeword of a memory are presented. The method includes detection and correction of an error in a bit of the codeword by an error deception and correction engine, storing error correction information of the error in a cache. In the second detection of the same error in the same bit the correction of the error is done based on the stored error correction information.
申请公布号 US2008148130(A1) 申请公布日期 2008.06.19
申请号 US20060638689 申请日期 2006.12.14
申请人 EILERT SEAN 发明人 EILERT SEAN
分类号 G11C29/00 主分类号 G11C29/00
代理机构 代理人
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