FREQUENCY AGILE PHASED LOCKED LOOP

摘要

A circuit having a frequency controllable oscillator and a variable time delay circuit. The time delay circuit is fed by a signal produced by the oscillator, such time delay circuit being coupled to the oscillator to control the frequency of the signal produced by the oscillator. The circuit allows frequency agility of a phase locked loop although locked to a common reference frequency. The PLL (17) is used in a phased array system as the phase shifter (15) for beamforming or beam steering. The phase shifts required for the antenna elements are generated by inserting a variable delay time circuit (20) into the feedback path of the corresponding PLL together with frequency dividers (36, 39).