COMPILED MEMORY, ASIC CHIP, AND LAYOUT METHOD FOR COMPILED MEMORY

摘要

Each memory block has word line groups composed of at least one word line, memory cells, and bit lines. A decoder section selects the connection control section corresponding to the memory block to be accessed and decodes address signals in order to select any of the word line groups. The logic of the decoder section is to assign the bits of the address signals for identifying the memory blocks and the connection control sections to a lower order than those of the address signals for identifying the word line groups. This makes it possible to equalize the number of word lines arranged in the memory blocks to each other to reduce the length of the bit lines. As a result, the wiring delay of the bit lines can be minimized to shorten the access time of the compiled memory.