<p>An SRAM device is composed of a field effect transistor having electrically separated logic signal input gate and a bias voltage input gate on the both surfaces of a standing fine semiconductor thin board, and includes a memory cell composed of a complementary transistor configuring two access transistors and a flip-flop circuit connected to a word line. A first bias voltage is inputted to the bias voltage input gate of the transistor configuring the memory cell in a row wherein the memory cell to be accessed for reading/writing is included, and a threshold voltage is set low to the logic signal input gate of the transistor. A second bias voltage is inputted to the bias voltage input gate of the transistor configuring the memory cell in a row wherein only the memory cell performing storage operation is included, and a threshold voltage is set high to the logic signal input gate of the transistor.</p>
申请公布号
WO2008069277(A1)
申请公布日期
2008.06.12
申请号
WO2007JP73605
申请日期
2007.12.06
申请人
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCEAND TECHNOLOGY;OUCHI, SHINICHI;LIU, YONGXUN;MASAHARA, MEISHOKU;MATSUKAWA, TAKASHI;ENDO, KAZUHIKO