LOW POWER CLOCK GATING CIRCUIT

摘要

A low power clock gating circuit is provided to realize a high speed and low power by using a low threshold voltage device and a high threshold voltage device, respectively. A low power clock gating circuit(450) comprises PMOS transistors and NMOS transistors. The PMOS transistors are electrically connected between a power terminal and a first inverter(402), between the power terminal and a second inverter(422), and between the power terminal and an end gate(444), respectively. The PMOS transistors are controlled by a sleep controlling signal applied through a sleep controlling terminal and have a high threshold voltage. The NMOS transistors are electrically connected between a ground and the first inverter, between the ground and the second inverter, and between the ground and the end gate, respectively. The NMOS transistors are controlled by the sleep controlling signal and have a high threshold voltage.