发明名称 Arrangement and method for testing a capacitance array in an integrated circuit
摘要 An arrangement for testing a plurality of capacitances in a capacitance array of an integrated circuit includes a power supply and a means for cyclically charging and discharging at least one of the capacitances. In this arrangement, the cycle frequency is dependent on the value of the capacitance. The cycle frequency or a quantity characteristic associated therewith is measured by a means to ascertain a value of the capacitance under test.
申请公布号 US7385404(B2) 申请公布日期 2008.06.10
申请号 US20040941428 申请日期 2004.09.15
申请人 INFINEON TECHNOLOGIES AG 发明人 PUMA GIUSEPPE LI;PHAM-STAEBNER DUYEN;WAGNER ELMAR
分类号 G01R31/12;G01R27/26;G01R31/27;G01R31/28;G01R31/3167;G01R31/3187;H03M1/10 主分类号 G01R31/12
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