发明名称 Method and apparatus for prefetching data to a lower level cache memory
摘要 A prefetching scheme to detect when a load misses the lower level cache and hits the next level cache. Consequently, the prefetching scheme utilizes the previous information for the cache miss to the lower level cache and hit to the next higher level of cache memory that may result in initiating a sidedoor prefetch load for fetching the previous or next cache line into the lower level cache. In order to generate an address for the sidedoor prefetch, a history of cache access is maintained in a queue.
申请公布号 US7383418(B2) 申请公布日期 2008.06.03
申请号 US20040933188 申请日期 2004.09.01
申请人 INTEL CORPORATION 发明人 JANIK KENNETH J.;VENKATRAMAN K S;ROHILLAH ANWAR;SPRANGLE ERIC;SINGHAL RONAK
分类号 G06F12/00;G06F9/26;G06F9/34 主分类号 G06F12/00
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