发明名称 |
CACHE AND CACHE BYPASS FUNCTIONAL METHOD |
摘要 |
<P>PROBLEM TO BE SOLVED: To enhance functions of a cache with respect to a cache and cache bypass functional method. <P>SOLUTION: A cache (104) for combining a processor (102) operatively with a main memory (106) is provided. The cache includes a cache memory (108) and a cache controller (110) combined operatively with this cache memory. The cache controller is composed so as to receive a memory request to be adapted to the cache memory or the main memory. Additionally, the cache controller is composed so that at least one memory request is made to be bypassed the cache memory by processing cache activity information. <P>COPYRIGHT: (C)2008,JPO&INPIT |
申请公布号 |
JP2008117388(A) |
申请公布日期 |
2008.05.22 |
申请号 |
JP20070275122 |
申请日期 |
2007.10.23 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT CO LP |
发明人 |
BRAIN D GAISER;KNEBEL PATRICK |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|