发明名称 Wafer level chip scale package
摘要 <p>A wafer level chip scale package is provided to simplify a manufacturing process by electrically connecting a bonding pad with a ball land using an anisotropic conductive film. A semiconductor chip(1) has a bonding pad(2), and an anisotropic conductive film(7) is attached to the semiconductor chip. The anisotropic conductive film has a wiring pattern(5) connected to the bonding pad of the semiconductor chip and having a ball land(3). A mounting member is attached to the ball land of the wiring pattern. The wiring pattern is formed by thermally pressing a heater block having a shape corresponding to the wiring pattern onto the anisotropic conductive film. The wiring pattern of the anisotropic conductive film is filled with solder paste(6).</p>
申请公布号 KR100826977(B1) 申请公布日期 2008.05.02
申请号 KR20060095089 申请日期 2006.09.28
申请人 发明人
分类号 H01L23/12 主分类号 H01L23/12
代理机构 代理人
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