| 摘要 |
A design structure. The design structure includes: a first set of FETs having a designed first V<SUB>t </SUB>and a second set of FETs having a designed second V<SUB>t</SUB>, the first V<SUB>t </SUB>different from the second V<SUB>t</SUB>; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.
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