| 摘要 |
FIELD: multi-threshold CMOS circuits and devices which function in active and waiting modes. ^ SUBSTANCE: integration circuit contains multi-threshold CMOS trigger, which conjugates CMOS circuits with low threshold level (LVT) and CMOS circuits with high threshold level (HVT). LVT circuits constitute the main part of trigger signal route circuits to guarantee high productivity of trigger. The trigger further contains HVT circuits to reduce leak currents in circuits with low threshold level, when the trigger is in waiting mode. One-phased trigger and two-phased trigger are claimed. Each trigger is realized with master and slave registers. Data is stored either in master or in slave register, depending on phase or phases or synchronization signals. In alternative case before the master register a multiplexer may be coupled to control the input signal route during waiting and active modes of trigger and to provide second input signal route for testing. ^ EFFECT: increased efficiency. ^ 6 cl, 10 dwg |
