| 摘要 |
Example embodiments are directed to a parallel bit test device and method using error correcting code. The parallel bit test device may include an error detecting and correcting unit configured to count the number of fail bits in an m-bit data signal, for example, by comparing bits of the m-bit data signal with corresponding bits of expected data, where m is a positive integer, and to output correction signals. The error detecting and correcting unit may be further configured to perform at least one logic operation on a correction control signal and comparison signals. The correction control signal may be generated in response to a test mode register set (TMRS) signal set and input by a user such that the logic level of the correction control signal may vary according to the counted number of fail bits. Each comparison signal may include information about a fail bit and the address of the fail bit.
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