| 摘要 |
PROBLEM TO BE SOLVED: To generate an interrupt signal to be input to one interrupt input terminal of a CPU based on a plurality of interrupt factors without deteriorating the processing speed or precision of the system. SOLUTION: This interrupt control circuit 11 is provided with a plurality of timers 110 to 113 to be started according to the rising or falling edge of a plurality of interrupt input signals to be generated from a plurality of interrupt factors and a logical sum gate 106 for acquiring the logical sum of the outputs of those plurality timers, and for inputting it to the interrupt input terminal of a CPU 10. An expiration time corresponding to the interrupt processing time of the corresponding interrupt factors is set in each timer. Each timer is started by the rising or falling edge of any interrupt input signal when the operation is not suppressed, and the interrupt signal is output to the logical sum means, and the operation of the other timers is suppressed until the lapse of the expiration time set in the timer. COPYRIGHT: (C)2008,JPO&INPIT
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