| 摘要 |
A hardware accelerator for a holographic image display system, the image display system being configured to generate a displayed image using a plurality of holographically generated temporal subframes, the temporal subframes being displayed sequentially in time such that they are perceived as a single reduced-noise image. Each said subframe is generated holographically by modulation of a spatial light modulator with holographic data such that replay of a hologram defined by said holographic data defines a subframe. The hardware accelerator comprises an input buffer to store image data defining an image for display, an output buffer to store holographic data for a the subframe, at least one hardware data processing module coupled to the input data buffer and output data buffer to process said image data to generate said holographic data for a subframe, and a controller to control the data processing module and to convey holographic data for a plurality of subframes corresponding to image data to said output data buffer. The hardware data processing module includes a binary quantiser to quantise one or both of a real component and an imaginary component of holographic data for each subframe. |
