| 摘要 |
An averaging circuit having an offset compensation circuit is provided to control an offset within a predetermined range by using a plurality of NMOS transistor pairs and a plurality of PMOS transistor pairs. An averaging circuit(500) comprises first(MP1,MP2), second(MP3,MP4), third(M1,M2), and fourth(M3,M4) transistor pairs having first, second, third, and fourth tail currents, respectively, and an offset compensation circuit(520,530) connected with tails of the first, second, third, and fourth transistors, respectively. The offset compensation circuit sinks the first and second tail currents to a ground line in response to a first control voltage(VCP), or the third and fourth tail currents to the ground line in response to a second control voltage(VCN). Output terminals of the first transistor pair are connected with output terminals of the second transistor pair, respectively, and output terminals of the third transistor pair are connected with output terminals of the fourth transistor pair, respectively.
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