| 摘要 |
A design structure comprising a digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock signal and a reference voltage, and generates a first output signal. The second differential comparator circuit receives the positive and negative differential clock signal, and generates a second output signal. The third differential comparator circuit receives the reference voltage and the negative differential clock signal, and generates a third output signal. A bus change-over detecting circuit receives the first output signal, and the third output signal, and generates an Enable signal. The digital clock generation circuit further includes a latch circuit which receives the second output signal, and the Enable signal and generates a digital clock signal. The latch circuit comprises a latch with glitch or noise immunity.
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