| 摘要 |
A delay-locked loop (DLL) circuit with mutual-interpolating architecture that provides multiple-phase clock generation is presented. Each delay-cell in the DLL circuit delay chain is effectively an interpolator that combines two input clock signals: one input clock signal is received from the output clock of previous stage in the delay chain, and the other input clock signal is fed back from a following stage. Each delay cell supports the concurrent functions of delay and interpolation. The architecture imposes a set of N simultaneous equations, where N is the total number of delay clock signals, to control the clock waveforms. These simultaneous equations obtain a unique solution when the DLL enters a lock state, and the generated delay clock signals inherently have a clock duty cycle of 50%. The delay chain can be implemented using either odd or even number of delay cells.
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