| 摘要 |
A clock switching circuit is provided to suppress a glitch in an output signal during a switching process by implementing a multiplexing circuit using a glitch-free multiplexer. A clock switching circuit receives at least two clocks, selects one of the clocks, and outputs the selected clock. The clock switching circuit includes a clock gating circuit(100) and a multiplexing circuit(200). The clock gating circuit outputs a gate input clock as a gate output clock or suppresses the gate input clock in response to a gate control signal. The multiplexing circuit receives the gate output clock and an external clock, selects one of the received clocks, and outputs the selected clock as the switching clock output. The gate control signal includes first and second control signals. The first control signal indicates whether a PLL(Phase Locked Loop) is locked. The second control signal selectively outputs the gate output clock, when the PLL is locked. |
