| 摘要 |
A carry lookahead adder is employed to determine an equality relationship and one or more inequality relationships between two operands. The carry lookahead adder includes a hierarchy of carry lookahead stages, each carry lookahead stage using either corresponding bits of the two operands or the carry generate values and carry propagate values from the prior stage to generate carry generate values and carry propagate values for use at the next stage. Equality logic receives a subset of the carry generate values and carry propagate values and, based on this subset of values, provides an equality relationship indicator that indicates the equality relationship between the two operands, or portions thereof. Further, inequality logic also receives a subset of the carry generate values and carry propagate values, and based on this subset of values, provides an inequality relationship indicator that indicates an inequality relationship between the two operands, or portions thereof.
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