CPU MODE-BASED CACHE ALLOCATION FOR IMAGE DATA

摘要

An apparatus includes a central processing unit (102) having an output to provide a status indicator (122), a graphics controller (104) having an output coupleable to a display interface, a cache (108) comprising a plurality of cache lines (1 18), and memory controller ( 106) having an input to receive the status indicator (122). The memory controller ( 106) is configured to disable allocation of cache lines (1 18) of the cache (108) for cache misses for data requests from the graphics controller (104) in response to the status indicator (122) indicating the central processing unit (102) is in an active mode. The memory controller ( 106) further is configured to enable allocation of cache lines (1 18) of the cache (108) for cache misses for data requests from the graphics controller ( 104) in response to the status indicator ( 122) indicating the central processing unit ( 102) is in an idle mode.