发明名称 SEMICONDUCTOR MEMORY, SYSTEM, TESTING METHOD FOR SYSTEM
摘要 A plurality of test patterns generated by a test pattern generating circuit are outputted from a first memory chip to test a different type second memory chip packaged in a same package as the first memory chip. Therefore, when the different type memory chips are mounted in the same package, even in a case where a terminal of the memory chip is not connected with an external terminal, the memory chip can be tested. Since there is no need for forming the external terminal which is useless for a system, system cost can be reduced. As a test apparatus which generates a complicated test pattern is not required, test cost can be reduced. The test pattern generating circuit is configured by employing nonvolatile logic, therefore, the test can be performed without preparing a test pattern. Thus, a user who purchases the first and the second memory chips for configuring the system is permitted to easily perform the test.
申请公布号 KR20080005425(A) 申请公布日期 2008.01.11
申请号 KR20077026599 申请日期 2005.04.21
申请人 FUJITSU LIMITED 发明人 UCHIDA TOSHIYA
分类号 H01L21/66 主分类号 H01L21/66
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