| 摘要 |
PROBLEM TO BE SOLVED: To attain an enhancement in a failure detection rate of a semiconductor integrated circuit, an increase in quality, and furthermore, shortening of a layout design period by performing an efficient and optimal layout design of the semiconductor integrated circuit. SOLUTION: In a layout 800, an output terminal 203S (a first cell) of a clock control circuit and an EN input terminal 204E of a GCB circuit 204 (a second cell) are connected through a cabling 1101, and the EN input terminal 204E of the GCB circuit 204 (the second cell) and a D input terminal of a FF circuit 206 (a cell for failure detection) are connected by cabling 1102. According to such a layout 800, since a signal outputted from the output terminal 203S (the first cell) is taken in the FF circuit 206 (the cell for failure detection) via the EN input terminal 204E of the cabling 1101 and the GCB circuit 204 (the second cell), a fault produced in an entire section on the clock control circuit and the cabling 1101 is detectable. COPYRIGHT: (C)2008,JPO&INPIT
|
